• | 2-stage pipeline enabling faster branch instruction execution with less clock cycles |
• | Single-cycle I/O & peripheral access reduce the number of clock cycles required enabling maximum CoreMark results with minimum power consumption |
• | Linear 4GB address-space removes complex paging schemes |
• | A micro trace buffer provides a simple, low-cost debugging solution that allows faster bug identification and correction without the need for additional I/O resources |
• | Upward compatible with Cortex-M3/4 cores and downward compatible to Cortex-M0 core. Broad ARM ecosystem support |